Showing posts with label Explained. Show all posts
Showing posts with label Explained. Show all posts
Friday, September 26, 2014
DC Voltage Doubler Circuit Explained
- The inverters, N3. . . N6, are connected in parallel and operate as a buffer stage to reduce the load- dependence of the circuit.
- Depending on the clock signal of the oscillator, point A in figure 1a is connected to the earth rail for a particular time per period and to the supply voltage for a particular time.
- This causes the voltage across capacitor C2 to rise to almost twice the supply voltage. If D1 is connected to earth and the -polarities of diodes D1, D2 and capacitors C1, C2 (figure 1b) are reversed, the output at A will be a negative voltage and, in the no load condition, it will be at the same level as the supply voltage.
- In both cases, unfortunately, the output voltage is dependent upon the load. As the load increases, the output voltage drops; in contrast, the superimposed a.c. level rises. The table shows the values measured in the circuit for load currents of 5 mA and 15mA.
- This simple circuit can produce a d.c. voltage which is approximately twice the supply voltage, in the no- load condition.
- Whilst point A is connected to earth, capacitors C1 and C2 charge up to the supply voltage via diodes D1 and D2. The oscillator then switches point A to the supply voltage potential during the remaining period, capacitor C1 transfers a part of its charge to capacitor C2.
- The 4049 IC contains a total of six inverters. Two of them, N1 and N2, form an oscillator together with R1 and C3, of which the frequency is about 10 kHz.
Thursday, September 25, 2014
Track and Hold Circuits Explained
Track and hold circuit using FET
When the switch is closed (or the FET conducting), circuit is behaving as an inverting amplifier with a gain of L?. As the inverting terminal of the op amp is a virtual earth, the capacitor is kept charged to the output voltage by the op amp.
When the 3 switch is opened (and the FET non- Q conducting) the voltage at the output is held constant by the capacitor, the current demands of the next stage being met by the op amp. Note that the value of C should be chosen such that its impedance at the operating frequency is. large compared to R1 and R2.
Track and hold circuit using opamps
When the control input is high the output tracks the input but when it goes low the output remains frozen at the value it was at the instant of transition. The operation of the circuit is generally self-evident and it may be regarded as two voltage followers, one consisting of two o- amps with the output following the input, the other is just the second op—amp which "foIlows" the voltage stored on the capacitor. lt is advisable to take care with the layout as with all op—amp circuits due to the huge open loop gain of these devices. The value chosen for C is a compromise between "siewing rate," that is the rate at which the circuit tracks a sudden change of input and "holding ability" which is the length of time, the circuit will hold a signal without unreasonable decay. To give some sort of guide, for a 10kHz square wave to the control input, a 0.01 p F capacitor seems to optimize the performance. The value of the resistors is also worth experimenting with.
When the switch is closed (or the FET conducting), circuit is behaving as an inverting amplifier with a gain of L?. As the inverting terminal of the op amp is a virtual earth, the capacitor is kept charged to the output voltage by the op amp.
When the 3 switch is opened (and the FET non- Q conducting) the voltage at the output is held constant by the capacitor, the current demands of the next stage being met by the op amp. Note that the value of C should be chosen such that its impedance at the operating frequency is. large compared to R1 and R2.
When the control input is high the output tracks the input but when it goes low the output remains frozen at the value it was at the instant of transition. The operation of the circuit is generally self-evident and it may be regarded as two voltage followers, one consisting of two o- amps with the output following the input, the other is just the second op—amp which "foIlows" the voltage stored on the capacitor. lt is advisable to take care with the layout as with all op—amp circuits due to the huge open loop gain of these devices. The value chosen for C is a compromise between "siewing rate," that is the rate at which the circuit tracks a sudden change of input and "holding ability" which is the length of time, the circuit will hold a signal without unreasonable decay. To give some sort of guide, for a 10kHz square wave to the control input, a 0.01 p F capacitor seems to optimize the performance. The value of the resistors is also worth experimenting with.
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