Thursday, September 25, 2014

Track and Hold Circuits Explained

Track and hold circuit using FET

When the switch is closed (or the FET conducting), circuit is behaving  as an inverting amplifier with a gain of L?. As the inverting terminal of the op amp is a virtual earth, the capacitor is kept charged to the output voltage by the op amp.
When the 3 switch is opened (and the FET non- Q conducting) the voltage at the output  is held constant by the capacitor, the current demands of the next stage being met by the op amp. Note that the value of C should be chosen such that its impedance at the operating frequency is. large compared to R1 and R2. 
Track and hold circuit using opamps

When the control  input is high the output tracks the  input but when it goes low the output remains frozen at the value it was at the instant of transition. The operation of the circuit is generally self-evident and it may be regarded as two voltage followers, one consisting of two o- amps with the output following the input, the other is just the second op—amp which "foIlows" the voltage stored on the capacitor. lt is advisable to take care with the layout as with all op—amp circuits due to the huge open loop gain of these devices. The value chosen for C is a compromise between "siewing rate," that is the rate at  which the circuit tracks a sudden change of input and "holding ability" which is the length of time, the circuit will hold a signal without unreasonable decay. To give some sort of  guide, for a 10kHz square wave to the control input, a 0.01 p F capacitor seems to optimize the performance. The value of the resistors is also worth experimenting with. 





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